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Texas Instruments /MSP432P401V /COMP_E1 /CExCTL2

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Interpret as CExCTL2

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15 1211 87 43 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0CEREF00 (CERSEL_0)CERSEL 0 (CERS_0)CERS 0CEREF10 (CEREFL_0)CEREFL 0 (CEREFACC_0)CEREFACC

CERS=CERS_0, CERSEL=CERSEL_0, CEREFL=CEREFL_0, CEREFACC=CEREFACC_0

Description

Comparator Control Register 2

Fields

CEREF0

Reference resistor tap 0
CERSEL

Reference select

0 (CERSEL_0): When CEEX = 0, VREF is applied to the V+ terminal; When CEEX = 1, VREF is applied to the V- terminal

1 (CERSEL_1): When CEEX = 0, VREF is applied to the V- terminal; When CEEX = 1, VREF is applied to the V+ terminal
CERS

Reference source

0 (CERS_0): No current is drawn by the reference circuitry

1 (CERS_1): VCC applied to the resistor ladder

2 (CERS_2): Shared reference voltage applied to the resistor ladder

3 (CERS_3): Shared reference voltage supplied to V(CREF). Resistor ladder is off
CEREF1

Reference resistor tap 1
CEREFL

Reference voltage level

0 (CEREFL_0): Reference amplifier is disabled. No reference voltage is requested

1 (CEREFL_1): 1.2 V is selected as shared reference voltage input

2 (CEREFL_2): 2.0 V is selected as shared reference voltage input

3 (CEREFL_3): 2.5 V is selected as shared reference voltage input
CEREFACC

Reference accuracy

0 (CEREFACC_0): Static mode

1 (CEREFACC_1): Clocked (low power, low accuracy) mode

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Register License

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data